From ee5053adcb30f03b20dfe03456be1f0a524a4d9a Mon Sep 17 00:00:00 2001 From: Zixun LI Date: Fri, 7 Nov 2025 16:02:23 +0100 Subject: [PATCH] mtd: rawnand: atmel: set pmecc data setup time Setup the pmecc data setup time as 3 clock cycles for 133MHz as recommended by the datasheet. Backported from Linux: f55f552a7c7e0a1 ("mtd: rawnand: atmel: set pmecc data setup time") Fixes: a490e1b7c017c ("nand: atmel: Add pmecc driver") Signed-off-by: Zixun LI Tested-by: Alexander Dahl Reviewed-by: Eugen Hristev --- drivers/mtd/nand/raw/atmel/pmecc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/nand/raw/atmel/pmecc.c b/drivers/mtd/nand/raw/atmel/pmecc.c index e500a0fe3f8..7c4e9bd5f99 100644 --- a/drivers/mtd/nand/raw/atmel/pmecc.c +++ b/drivers/mtd/nand/raw/atmel/pmecc.c @@ -142,6 +142,7 @@ struct atmel_pmecc_caps { int nstrengths; int el_offset; bool correct_erased_chunks; + bool clk_ctrl; }; struct atmel_pmecc_user_conf_cache { @@ -840,6 +841,10 @@ atmel_pmecc_create(struct udevice *dev, pmecc->regs.timing = 0; + /* pmecc data setup time */ + if (caps->clk_ctrl) + writel(PMECC_CLK_133MHZ, pmecc->regs.base + ATMEL_PMECC_CLK); + /* Disable all interrupts before registering the PMECC handler. */ writel(0xffffffff, pmecc->regs.base + ATMEL_PMECC_IDR); atmel_pmecc_reset(pmecc); @@ -884,6 +889,7 @@ static struct atmel_pmecc_caps at91sam9g45_caps = { .strengths = atmel_pmecc_strengths, .nstrengths = 5, .el_offset = 0x8c, + .clk_ctrl = true, }; static struct atmel_pmecc_caps sama5d4_caps = { -- 2.47.3