From ed8dfc46e0099540cb923f61bca885b460f1365e Mon Sep 17 00:00:00 2001
From: Yonghong Song <ysong@broadcom.com>
Date: Sat, 21 Dec 2013 16:52:16 +0530
Subject: [PATCH] MIPS: Netlogic: L1D cacheflush before thread enable on XLPII

On XLPII CPUs, the L1D cache has to be flushed with regular cache
operations before enabling threads in a core.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6276/
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