From ece509c10985ba93ccc8c68f808a9e767250041c Mon Sep 17 00:00:00 2001
From: Dylan Reid <dgreid@chromium.org>
Date: Mon, 3 Nov 2014 10:28:56 -0800
Subject: [PATCH] ASoC: max98090: Correct pclk divisor settings

The Baytrail-based chromebooks have a 20MHz mclk, the code was setting
the divisor incorrectly in this case.  According to the 98090
datasheet, the divisor should be set to DIV1 for 10 <= mclk <= 20.
Correct this and the surrounding clock ranges as well to match the
datasheet.

Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
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