From eb65c25b611887ed57ec38ef8f61af80e76b7beb Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 28 Feb 2025 20:02:23 +0200 Subject: [PATCH] video: tegra20: implement a minimal HOST1X driver for essential clock and reset setup Introduce a simplified HOST1X driver, limited to the basic clock and reset initialization of the bus. Signed-off-by: Svyatoslav Ryhel --- drivers/video/tegra20/Kconfig | 5 ++ drivers/video/tegra20/Makefile | 1 + drivers/video/tegra20/tegra-dc.c | 5 -- drivers/video/tegra20/tegra-host1x.c | 86 ++++++++++++++++++++++++++++ 4 files changed, 92 insertions(+), 5 deletions(-) create mode 100644 drivers/video/tegra20/tegra-host1x.c diff --git a/drivers/video/tegra20/Kconfig b/drivers/video/tegra20/Kconfig index f5c4843e119..d7c402e95fd 100644 --- a/drivers/video/tegra20/Kconfig +++ b/drivers/video/tegra20/Kconfig @@ -1,6 +1,11 @@ +config HOST1X_TEGRA + bool "NVIDIA Tegra host1x BUS support" + depends on SIMPLE_BUS + config VIDEO_TEGRA20 bool "Enable Display Controller support on Tegra20 and Tegra 30" depends on OF_CONTROL + select HOST1X_TEGRA help T20/T30 support video output to an attached LCD panel as well as other options such as HDMI. Only the LCD is supported in U-Boot. diff --git a/drivers/video/tegra20/Makefile b/drivers/video/tegra20/Makefile index a75aea2a875..c0fd42a72d5 100644 --- a/drivers/video/tegra20/Makefile +++ b/drivers/video/tegra20/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_HOST1X_TEGRA) += tegra-host1x.o obj-$(CONFIG_VIDEO_TEGRA20) += tegra-dc.o obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o tegra-mipi.o mipi-phy.o obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += tegra-pwm-backlight.o diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c index 16a2b5281bf..001967f2a5a 100644 --- a/drivers/video/tegra20/tegra-dc.c +++ b/drivers/video/tegra20/tegra-dc.c @@ -319,11 +319,6 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv, / priv->pixel_clock) - 2; log_debug("Display clock %lu, divider %lu\n", rate, priv->scdiv); - /* - * HOST1X is init by default at 150MHz with PLLC as parent - */ - clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL, - 150 * 1000000); clock_start_periph_pll(priv->clk->id, priv->clk_parent->id, rate); diff --git a/drivers/video/tegra20/tegra-host1x.c b/drivers/video/tegra20/tegra-host1x.c new file mode 100644 index 00000000000..58ab871a3b4 --- /dev/null +++ b/drivers/video/tegra20/tegra-host1x.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Svyatoslav Ryhel + */ + +#include +#include +#include +#include +#include + +#include +#include + +struct tegra_host1x_info { + u32 clk_parent; + u32 rate; +}; + +static int tegra_host1x_probe(struct udevice *dev) +{ + struct clk *clk; + struct reset_ctl reset_ctl; + const struct tegra_host1x_info *info; + int ret; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) { + log_debug("%s: cannot get HOST1X clock: %ld\n", + __func__, PTR_ERR(clk)); + return PTR_ERR(clk); + } + + ret = reset_get_by_name(dev, "host1x", &reset_ctl); + if (ret) { + log_debug("%s: cannot get HOST1X reset: %d\n", + __func__, ret); + return ret; + } + + info = (struct tegra_host1x_info *)dev_get_driver_data(dev); + + reset_assert(&reset_ctl); + clock_start_periph_pll(clk->id, info->clk_parent, info->rate); + + mdelay(2); + reset_deassert(&reset_ctl); + + return 0; +} + +static const struct tegra_host1x_info tegra20_host1x_info = { + .clk_parent = CLOCK_ID_CGENERAL, + .rate = 150000000, /* 150 MHz */ +}; + +static const struct tegra_host1x_info tegra114_host1x_info = { + .clk_parent = CLOCK_ID_PERIPH, + .rate = 136000000, /* 136 MHz */ +}; + +static const struct udevice_id tegra_host1x_ids[] = { + { + .compatible = "nvidia,tegra20-host1x", + .data = (ulong)&tegra20_host1x_info + }, { + .compatible = "nvidia,tegra30-host1x", + .data = (ulong)&tegra20_host1x_info + }, { + .compatible = "nvidia,tegra114-host1x", + .data = (ulong)&tegra114_host1x_info + }, { + .compatible = "nvidia,tegra124-host1x", + .data = (ulong)&tegra114_host1x_info + }, { + /* sentinel */ + } +}; + +U_BOOT_DRIVER(tegra_host1x) = { + .name = "tegra_host1x", + .id = UCLASS_SIMPLE_BUS, + .of_match = tegra_host1x_ids, + .probe = tegra_host1x_probe, + .flags = DM_FLAG_PRE_RELOC, +}; -- 2.39.5