From d584c1331d6421e2387eab10b11fa6f08b4a4b5f Mon Sep 17 00:00:00 2001
From: =?utf8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
Date: Mon, 23 Dec 2013 00:32:37 -0300
Subject: [PATCH] clk: sunxi: add PLL5 and PLL6 support
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This commit implements PLL5 and PLL6 support on the sunxi clock driver.
These PLLs use a similar factor clock, but differ on their outputs.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
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