From ce8f407a3cc7fc58804b9135e7c8780f0f8c2a8d Mon Sep 17 00:00:00 2001
From: Hariprasad Shenai <hariprasad@chelsio.com>
Date: Fri, 7 Nov 2014 17:06:30 +0530
Subject: [PATCH] cxgb4/cxgb4vf: For T5 use Packing and Padding Boundaries for
 SGE DMA transfers

T5 introduces the ability to have separate Packing and Padding Boundaries
for SGE DMA transfers from the chip to Host Memory. This change set takes
advantage of that to set up a smaller Padding Boundary to conserve PCI Link
and Memory Bandwidth with T5.

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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