From c98f50628722e2e287656bc7e7492e3d3a0726b8 Mon Sep 17 00:00:00 2001
From: Akash Goel <akash.goel@intel.com>
Date: Mon, 24 Mar 2014 23:00:07 +0530
Subject: [PATCH] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for
 vlv

For disabling L3 clock gating we need to set bit 25 of MMIO
register 940c. Earlier this was being done by just writing 1
into bit 25 and resetting all other bits.
This patch modifies the routine to read-modify-write of the
register, so that the values of other bits are not destroyed.

v2: Modifying the comments and the patch commit message (Chris)

Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Apply checkpatch fixup.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
Reading git-format-patch failed