From c44b56af9ca3a6f135d8f22b9a240f53909b371e Mon Sep 17 00:00:00 2001
From: Nicolin Chen <Guangyu.Chen@freescale.com>
Date: Wed, 23 Jul 2014 19:23:39 +0800
Subject: [PATCH] ASoC: fsl_sai: Don't reset FIFO until TE/RE bit is unset

TE/RE bit of T/RCSR will remain set untill the current frame is physically
finished. The FIFO reset operation should wait this bit's totally cleared
rather than ignoring its status which might cause TE/RE disabling failed.

This patch adds delay and timeout to wait for its completion before FIFO
reset.

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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