From bfa709bc823fc32ee8dd5220d1711b46078235d8 Mon Sep 17 00:00:00 2001
From: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Date: Tue, 18 Mar 2014 13:41:25 +0800
Subject: [PATCH] cpufreq: powerpc: add cpufreq transition latency for FSL
 e500mc SoCs

According to the data provided by HW Team, at least 12 internal platform
clock cycles are required to stabilize a DFS clock switch on FSL e500mc Socs.
This patch replaces the CPUFREQ_ETERNAL with appropriate HW clock transition
latency to make DFS governors work normally on Freescale e500mc boards.

Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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