From bbf2ba67cdbdb3676a661c3eba5572d1e513627f Mon Sep 17 00:00:00 2001
From: Kevin Cernekee <cernekee@gmail.com>
Date: Mon, 20 Oct 2014 21:27:58 -0700
Subject: [PATCH] MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x
 and 5000 CPUs

BMIPS438x has a 64-byte D$ line size and BMIPS5000 has a 128-byte L2
line size.  If L1_CACHE_SHIFT is undersized, DMA buffers will not be
cacheline-aligned and terrible things will happen.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8164/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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