From b9b8e614b5805a99a5484c3d44fbfebaa8de4c65 Mon Sep 17 00:00:00 2001
From: Gabriel FERNANDEZ <gabriel.fernandez@st.com>
Date: Thu, 27 Feb 2014 16:24:15 +0100
Subject: [PATCH] clk: st: Support for PLLs inside ClockGenA(s)

The patch supports the c65/c32 type PLLs used by ClockGenA(s)

PLL clock : It includes support for all c65/c32 type PLLs
inside ClockGenA(s) : implemented as Fixed Parent / Fixed Rate clock,
with clock rate calculated reading H/w settings done at BOOT.

c65 PLLs have 2 outputs : HS and LS
c32 PLLs have 1-4 outputs : ODFx

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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