From af951761d01c89eea8f1dcccf8010218e4b55817 Mon Sep 17 00:00:00 2001 From: "ludovic.desroches@atmel.com" Date: Thu, 17 Sep 2015 10:16:19 +0200 Subject: [PATCH] mmc: sdhci: add quirk SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST The Atmel sdhci device needs a new quirk. sdhci_set_clock set the Clock Control Register to 0 before computing the new value and writing it. It disables the internal clock which causes a reset mecanism. If we write the new value before this reset mecanism is done, it will prevent the stabilisation of the internal clock, so a delay is needed. This delay is about 2-3 cycles of the base clock. To be safe, a 1 ms delay is used. Signed-off-by: Ludovic Desroches Signed-off-by: Ulf Hansson --- Reading git-format-patch failed