From a9da9bce88ee842c7904b5670c035ca759e77238 Mon Sep 17 00:00:00 2001
From: Gaurav K Singh <gaurav.k.singh@intel.com>
Date: Fri, 5 Dec 2014 14:13:41 +0530
Subject: [PATCH] drm/i915: Pixel Clock changes for DSI dual link

For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for extra pixels.

v2 : Address review comments by Jani
     - Removed the bit mask used for ->dual_link
     - Used DSI instead of MIPI for #define variables

v3: Added the VLV_DISPLAY_BASE to VLV_CHICKEN_3 register

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
Reading git-format-patch failed