From a8f3ef6197979824ee117d89a26c57e347c62731 Mon Sep 17 00:00:00 2001 From: Sonika Jindal Date: Thu, 5 Mar 2015 10:02:30 +0530 Subject: [PATCH] drm/i915/skl: Add support for edp 1.4 intermediate frequencies MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit eDp 1.4 supports custom frequencies. Skylake supports following intermediate frequencies : 3.24 GHz, 2.16 GHz and 4.32 GHz along with usual LBR, HBR and HBR2 frequencies. Read sink supported frequencies and get common frequencies from sink and source and use these for link training. v2: Rebased, removed calculation of min_clock since for edp it is taken as max_clock (as per comment). v3: Keeping single array for link rates (Satheesh) v4: Setting LINK_BW_SET to 0 when setting LINK_RATE_SET (Satheesh) v5: Some minor nits (Ville) v6: Keeping separate arrays for source and sink rates (Ville) v7: Remove redundant setting of DP_LINK_BW_SET to 0 (Ville) Reviewed-by: Ville Syrjälä Signed-off-by: Sonika Jindal Signed-off-by: Daniel Vetter --- Reading git-format-patch failed