From 9e60121fd18c22851c19ec04e8e58172cb5a7d2c Mon Sep 17 00:00:00 2001
From: Paul Walmsley <pwalmsley@nvidia.com>
Date: Fri, 7 Jun 2013 06:19:01 -0600
Subject: [PATCH] clk: tegra: T114: add DFLL source clocks

Add the input clocks needed by the DFLL IP blocks.  Initialize them to
51MHz (as required by the DFLL GFD) and to use the PLL_P clock source.

This patch is a collaboration with Peter De Schrijver
<pdeschrijver@nvidia.com>.

Thanks to Laxman Dewangan <ldewangan@nvidia.com> for identifying the
requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout
issues.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Andrew Chew <achew@nvidia.com>
Cc: Matthew Longnecker <mlongnecker@nvidia.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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