From 9dc4f4fbc02ca22f519a8f0a8ae3a837af761f56 Mon Sep 17 00:00:00 2001 From: Aaron Carroll Date: Sat, 29 Jan 2011 00:52:12 +0530 Subject: [PATCH] omap4430panda: enable clock gating for M6_DPLL_CORE The M6 clock from the core DPLL supplies a clock to the debug domain. After the core DPLL is locked, the M6 clock appears to stop if clock gating has been *disabled* for that output (reason unknown). This breaks JTAG debugging. This patch enables clock gating on M6_DPLL_CORE before locking the core DPLL, so the debugger continues to work. Signed-off-by: Aaron Carroll Signed-off-by: Anand Gadiyar --- board/omap4430panda/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c index 792e5d6..2256b32 100644 --- a/board/omap4430panda/clock.c +++ b/board/omap4430panda/clock.c @@ -445,7 +445,7 @@ static void configure_core_dpll(clk_index) sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x0); sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); } @@ -504,7 +504,7 @@ void configure_core_dpll_no_lock(void) sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x0); sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); // } -- 2.39.5