From 97833f4cf6f681a341e76771bbf42bc8f8611d82 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Sat, 3 May 2025 04:52:52 -0700 Subject: [PATCH] riscv: starfive: jh7110: move uart0 clock frequency to config header Move unnecessary clock frequency assignment out of device-tree and into the board config header so that the ns16550 serial driver can successfully init during SPL after failing to resolve the parent clock from upstream dts. The serial driver will then resolve clock frequency from device-tree node parent clock at init during Main app as it is expected by upstream. Signed-off-by: E Shattow Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-common-u-boot.dtsi | 1 - include/configs/starfive-visionfive2.h | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi index 6d85b2d91a7..049b0a7ce28 100644 --- a/arch/riscv/dts/jh7110-common-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi @@ -27,7 +27,6 @@ bootph-pre-ram; reg-offset = <0>; current-speed = <115200>; - clock-frequency = <24000000>; }; &mmc0 { diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index 049b0a06301..e7001b26abf 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -39,4 +39,6 @@ "partitions=" PARTS_DEFAULT "\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" +#define CFG_SYS_NS16550_CLK 24000000 + #endif /* _STARFIVE_VISIONFIVE2_H */ -- 2.39.5