From 922044c9dfec40d5adc5d4a757f802e55e3d0a85 Mon Sep 17 00:00:00 2001
From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Fri, 14 Feb 2014 14:18:57 +0200
Subject: [PATCH] drm/i915: Avoid div by zero when pixel clock is large
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Make sure the line_time_us isn't zero in the gmch watermarks code as
that would cause a div by zero. This can be triggered by specifying
a very fast pixel clock for the mode.

At some point we should probably just switch over to using the same
math we use on PCH platforms which avoids such intermediate rounded
results.

Also we should verify the user provided mode much more rigorously.
At the moment we accept pretty much anything.

Note that "very fast mode" here means above 74.25 GHz.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Add Ville's clarification of what "very fast" means.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
Reading git-format-patch failed