From 8fc48d1a01acec2568b48b2afd6303397af593c8 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Mon, 7 Apr 2025 19:56:15 +0200 Subject: [PATCH] clk/qcom: apq8096: fix the sdhci clock Select the right clock for sdhci. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Caleb Connolly Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250407175617.3494506-3-jorge.ramirez@oss.qualcomm.com Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-apq8096.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index bc00826a5e8..551f52d5197 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -83,7 +83,7 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate) struct msm_clk_priv *priv = dev_get_priv(clk->dev); switch (clk->id) { - case GCC_SDCC1_APPS_CLK: /* SDC1 */ + case GCC_SDCC2_APPS_CLK: /* SDC2 */ return clk_init_sdc(priv, rate); break; case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/ -- 2.39.5