From 8b3f2eb7d8912204bda2d914b8a9a1ce1c31bb5c Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 30 Mar 2025 18:24:21 +0200 Subject: [PATCH] riscv: dts: jh7110: add bootph-pre-ram for &pllclk Since commit f98cd471f06b ("clk: clk-composite: Resolve parent clock by name") the StarFive VisionFive 2 board fails to boot. Before that patch the SPL debug UART showed warnings like: clk_register: failed to get pll0_out device (parent of perh_root) clk_register: failed to get pll0_out device (parent of qspi_ref_src) clk_register: failed to get pll0_out device (parent of usb_125m) clk_register: failed to get pll0_out device (parent of gmac_src) clk_register: failed to get pll0_out device (parent of gmac1_gtxclk) clk_register: failed to get pll0_out device (parent of gmac0_gtxclk) The &pllclk clock needs to be enabled early. Fixes: f98cd471f06b ("clk: clk-composite: Resolve parent clock by name") Suggested-by: Marek Vasut Tested-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang Signed-off-by: Heinrich Schuchardt --- arch/riscv/dts/jh7110-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index ce7d9e16961..a9e318c4a31 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -102,6 +102,10 @@ bootph-pre-ram; }; +&pllclk { + bootph-pre-ram; +}; + &syscrg { bootph-pre-ram; }; -- 2.39.5