From 7ea653efa98d8144345227576fc084ed7a356cf8 Mon Sep 17 00:00:00 2001
From: Philipp Zabel <p.zabel@pengutronix.de>
Date: Mon, 24 Feb 2014 14:51:50 +0100
Subject: [PATCH] ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable,
 increase IPU priority

This is needed so that the IPU framebuffer scanout cannot be
starved by VPU or GPU activity.
Some boards like the SabreLite and SabreSD seem to set this in
the DCD already, but the documented register reset values do not
contain the necessary settings.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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