From 7e3bc3a98fd1df5839cdc5cbce4dfdb9e4c03655 Mon Sep 17 00:00:00 2001 From: Sean Paul Date: Tue, 7 Oct 2014 16:04:42 +0200 Subject: [PATCH] drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlier Make sure the DSI PHY_TIMING and BTA_TIMING registers are initialized when the clocks are set up as opposed to when the output is enabled. This makes sure that the PHY timings are properly set up when the panel is prepared and that DCS commands sent at that time use the appropriate timings. Signed-off-by: Sean Paul Signed-off-by: Thierry Reding --- Reading git-format-patch failed