From 73bbf6bd907906dcbdc78f3af38a722c0fe498d8 Mon Sep 17 00:00:00 2001
From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Fri, 21 Nov 2014 21:54:25 +0200
Subject: [PATCH] drm/i915: Fix gen4 GPU reset
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On pre-ctg the reset bit directly controls the reset signal. We must
assert it for >=20usec and then deassert it. Bit 1 is a RO status bit
which should also go down when the reset is no longer asserted.

Tested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Reading git-format-patch failed