From 738c05c07d74769a1c5704636969b9b21cc96835 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Wed, 19 Nov 2014 16:25:37 +0200 Subject: [PATCH] drm/i915: vlv: fix cdclk setting during modeset while suspended MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Currently after doing DPMS-OFF on all outputs CDCLK won't be set to its minimum value as it should. A subsequent modeset to turn off all outputs will thus run with all power domains disabled, and notice that it needs to change CDCLK to its minimum value. Since the power domains are disabled this will emit a register-access-while-suspended WARN and fail to set the minimum freq. The proper solution for this is to set the minimum frequency during DPMS-OFF. That needs a bigger rework that would take into account the user DPMS setting too during the calculation of the new modesetting configuration. Until that's done this stop-gap solution gets the PIPE-A power domain during setting the CDCLK; this domain covers the HW blocks needed for this. Idea to use PIPE-A domain from Ville. Testcase: igt/pm_rpm Reference: https://bugs.freedesktop.org/show_bug.cgi?id=82939 Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- Reading git-format-patch failed