From 720023c85f0c5e78893536e137994bcca1b70282 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 26 Feb 2025 11:37:12 +0000 Subject: [PATCH] sunxi: sun50i_h6: clock: fix PLL_PERIPH0 rate calculation MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit On the Allwinner D1/R528/T113-s3 SoCs (NCAT2) the factors encoded in the PLL register describe the doubled clock rate, as in the other SoCs. Correct for that by always dividing the calculated rate by 2, except on the H6, where we need a divisor of 4 (no change here). This corrects the PERIPH0 clock rate as read by the MMC driver, and actually doubles the MMC performance on those NCAT2 chips. Signed-off-by: Andre Przywara Reported-by: Kuba Szczodrzyński Reviewed-by: Jernej Skrabec Reviewed-by: Peng Fan --- arch/arm/mach-sunxi/clock_sun50i_h6.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index b424a7893ea..359513d1669 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -147,15 +147,20 @@ unsigned int clock_get_pll6(void) if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >> CCM_PLL6_CTRL_P0_SHIFT) + 1; - m = 1; } else { div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> CCM_PLL6_CTRL_DIV1_SHIFT) + 1; - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) - m = 4; - else - m = 2; } + /* + * The factors encoded in the register describe the doubled clock + * frequency, expect for the H6, where it's the quadrupled frequency. + * Compensate for that here. + */ + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + m = 4; + else + m = 2; + return 24000000U * n / m / div1 / div2; } -- 2.39.5