From 6033a949b2c466a13e84daebd99fdca5960b4db5 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Thu, 14 Nov 2013 14:41:32 -0800 Subject: [PATCH] mtd: nand: pxa3xx: make ECC configuration checks more explicit The Armada BCH configuration in this driver uses one of the two following ECC schemes: 16-bit correction per 2048 bytes 16-bit correction per 1024 bytes These are sufficient for mapping to the 4-bit per 512-bytes and 8-bit per 512-bytes (respectively) minimum correctability requirements of many common NAND. The current code only checks for the required strength (4-bit or 8-bit) without checking the ECC step size that is associated with that strength (and simply assumes it is 512). While that is often a safe assumption to make, let's make it explicit, since we have that information. Signed-off-by: Brian Norris Acked-by: Ezequiel Garcia Tested-by: Daniel Mack --- Reading git-format-patch failed