From 5b6b7490af110c2b0df807eddd00ae6290bcf50a Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 15 Jul 2014 14:59:21 -0700 Subject: [PATCH] clk: qcom: Fix PLL rate configurations Sometimes we need to program PLLs with a fixed rate configuration during driver probe. Doing this after we register the PLLs with the clock framework causes the common clock framework to assume the rate of the PLLs are 0. This causes all sorts of problems for rate recalculations because the common clock framework caches the rate once at registration time unless a flag is set to always recalculate the rates. Split the qcom_cc_probe() function into two pieces, map and everything else, so that drivers which need to configure some PLL rates or otherwise twiddle bits in the clock controller can do so before registering clocks. This allows us to properly detect the rates of PLLs that are programmed at boot. Fixes: 49fc825f0cc2 "clk: qcom: Consolidate common probe code" Signed-off-by: Stephen Boyd --- Reading git-format-patch failed