From 58ef50ff9af1ac64fbfdc05188e8f053bef811c4 Mon Sep 17 00:00:00 2001
From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@intel.com>
Date: Tue, 18 Feb 2025 16:34:50 +0800
Subject: [PATCH] drivers: clk: agilex5: Set PLL to asynchronous mode

PLL frequency would overshoot from the original target in
synchronous mode during low VCC voltage condition.

To resolve this issue, PLL is set to run on asynchronous mode
instead of enabling synchronous mode in the clock driver.

Signed-off-by: Muhammad Hazim Izzat Zamri <muhammad.hazim.izzat.zamri@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
---
 drivers/clk/altera/clk-agilex5.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c
index a284b562486..fb1e72ffc5c 100644
--- a/drivers/clk/altera/clk-agilex5.c
+++ b/drivers/clk/altera/clk-agilex5.c
@@ -72,15 +72,6 @@ static const struct {
 	u32 val;
 	u32 mask;
 } membus_pll[] = {
-	{
-		MEMBUS_CLKSLICE_REG,
-		/*
-		 * BIT[7:7]
-		 * Enable source synchronous mode
-		 */
-		BIT(7),
-		BIT(7)
-	},
 	{
 		MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG,
 		/*
-- 
2.39.5