From 55c4a6db549cdad3f185e33f439d130cec7a6bc8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 May 2025 00:03:40 +0200 Subject: [PATCH] arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support Add Retronix R-Car V4H Sparrow Hawk board based on Renesas R-Car V4H ES3.0 (R8A779G3) SoC. This is a single-board computer with single gigabit ethernet, DSI-to-eDP bridge, DSI and two CSI2 interfaces, audio codec, two CANFD ports, micro SD card slot, USB PD supply, USB 3.0 ports, M.2 Key-M slot for NVMe SSD, debug UART and JTAG. DT is imported from Linux next commit: a719915e76f2 ("arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support") Signed-off-by: Marek Vasut --- .../arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi | 50 ++ arch/arm/mach-renesas/Kconfig.rcar4 | 7 + board/renesas/sparrowhawk/Kconfig | 15 + board/renesas/sparrowhawk/MAINTAINERS | 7 + board/renesas/sparrowhawk/Makefile | 9 + board/renesas/sparrowhawk/sparrowhawk.c | 143 ++++ configs/r8a779g3_sparrowhawk_defconfig | 69 ++ doc/board/renesas/renesas.rst | 6 + .../arm64/renesas/r8a779g3-sparrow-hawk.dts | 666 ++++++++++++++++++ include/configs/sparrowhawk.h | 14 + 10 files changed, 986 insertions(+) create mode 100644 arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi create mode 100644 board/renesas/sparrowhawk/Kconfig create mode 100644 board/renesas/sparrowhawk/MAINTAINERS create mode 100644 board/renesas/sparrowhawk/Makefile create mode 100644 board/renesas/sparrowhawk/sparrowhawk.c create mode 100644 configs/r8a779g3_sparrowhawk_defconfig create mode 100644 dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk.dts create mode 100644 include/configs/sparrowhawk.h diff --git a/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi new file mode 100644 index 00000000000..c9f302799f1 --- /dev/null +++ b/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the R-Car V4H Sparrow Hawk board + * + * Copyright (C) 2025 Marek Vasut + */ + +#include "r8a779g0-u-boot.dtsi" + +/* Page 31 / FAN */ +&gpio1 { + pwm-fan-hog { + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PWM-FAN"; + }; +}; + +/* Page 29 / CSI_IF_CN / CAM_CN0 */ +&i2c1 { + status = "okay"; +}; + +/* Page 29 / CSI_IF_CN / CAM_CN1 */ +&i2c2 { + status = "okay"; +}; + +/* Page 31 / IO_CN */ +&i2c3 { + status = "okay"; +}; + +/* Page 31 / IO_CN */ +&i2c4 { + status = "okay"; +}; + +/* Page 18 / POWER_CORE and Page 19 / POWER_PMIC */ +&i2c5 { + status = "okay"; +}; + +&rpc { + flash@0 { + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; diff --git a/arch/arm/mach-renesas/Kconfig.rcar4 b/arch/arm/mach-renesas/Kconfig.rcar4 index c42bb9765ef..04418f7aa05 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar4 +++ b/arch/arm/mach-renesas/Kconfig.rcar4 @@ -66,6 +66,12 @@ config TARGET_WHITEHAWK help Support for Renesas R-Car Gen4 White Hawk platform +config TARGET_SPARROWHAWK + bool "Sparrow Hawk board" + imply R8A779G0 + help + Support for Renesas R-Car Gen4 Sparrow Hawk platform + config TARGET_GRAYHAWK bool "Gray Hawk board" imply R8A779H0 @@ -78,6 +84,7 @@ source "board/renesas/falcon/Kconfig" source "board/renesas/spider/Kconfig" source "board/renesas/s4sk/Kconfig" source "board/renesas/whitehawk/Kconfig" +source "board/renesas/sparrowhawk/Kconfig" source "board/renesas/grayhawk/Kconfig" endif diff --git a/board/renesas/sparrowhawk/Kconfig b/board/renesas/sparrowhawk/Kconfig new file mode 100644 index 00000000000..6b7aba348df --- /dev/null +++ b/board/renesas/sparrowhawk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SPARROWHAWK + +config SYS_SOC + default "renesas" + +config SYS_BOARD + default "sparrowhawk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "sparrowhawk" + +endif diff --git a/board/renesas/sparrowhawk/MAINTAINERS b/board/renesas/sparrowhawk/MAINTAINERS new file mode 100644 index 00000000000..9f759aefab8 --- /dev/null +++ b/board/renesas/sparrowhawk/MAINTAINERS @@ -0,0 +1,7 @@ +SPARROWHAWK BOARD +M: Marek Vasut +S: Maintained +F: arch/arm/dts/r8a779g3* +F: board/renesas/sparrowhawk/ +F: configs/r8a779g3_sparrowhawk_defconfig +F: include/configs/sparrowhawk.h diff --git a/board/renesas/sparrowhawk/Makefile b/board/renesas/sparrowhawk/Makefile new file mode 100644 index 00000000000..90da9e02537 --- /dev/null +++ b/board/renesas/sparrowhawk/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/sparrowhawk/Makefile +# +# Copyright (C) 2025 Marek Vasut +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sparrowhawk.o diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c new file mode 100644 index 00000000000..8e72b5424d1 --- /dev/null +++ b/board/renesas/sparrowhawk/sparrowhawk.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Marek Vasut + */ + +#include +#include +#include +#include + +#if defined(CONFIG_XPL_BUILD) + +static const struct renesas_dbsc5_board_config +renesas_v4h_sparrowhawk_8g_6400_dbsc5_board_config = { + /* RENESAS V4H Sparrow Hawk (64Gbit 1rank) */ + .bdcfg_phyvalid = 0xF, + .bdcfg_vref_r = 0x0, + .bdcfg_vref_w = 0x0, + .bdcfg_vref_ca = 0x0, + .bdcfg_rfm_chk = true, + .ch = { + [0] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x04506132, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x26157084, 0x12306854 }, + .bdcfg_dm_swap = { 0x03, 0x07 }, + .bdcfg_cs_swap = 0x10 + }, + [1] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x02431065, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x56782314, 0x70423856 }, + .bdcfg_dm_swap = { 0x00, 0x01 }, + .bdcfg_cs_swap = 0x10 + }, + [2] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x02150643, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x58264031, 0x40587236 }, + .bdcfg_dm_swap = { 0x07, 0x01 }, + .bdcfg_cs_swap = 0x10 + }, + [3] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x01546230, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x45761328, 0x68023745 }, + .bdcfg_dm_swap = { 0x00, 0x01 }, + .bdcfg_cs_swap = 0x10 + } + } +}; + +static const struct renesas_dbsc5_board_config +renesas_v4h_sparrowhawk_16g_5500_dbsc5_board_config = { + /* RENESAS V4H Sparrow Hawk (64Gbit 2rank) */ + .bdcfg_phyvalid = 0xF, + .bdcfg_vref_r = 0x0, + .bdcfg_vref_w = 0x0, + .bdcfg_vref_ca = 0x0, + .bdcfg_rfm_chk = true, + .ch = { + [0] = { + .bdcfg_ddr_density = { 0x06, 0x06 }, + .bdcfg_ca_swap = 0x04506132, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x26157084, 0x12306854 }, + .bdcfg_dm_swap = { 0x03, 0x07 }, + .bdcfg_cs_swap = 0x10 + }, + [1] = { + .bdcfg_ddr_density = { 0x06, 0x06 }, + .bdcfg_ca_swap = 0x02431065, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x56782314, 0x70423856 }, + .bdcfg_dm_swap = { 0x00, 0x01 }, + .bdcfg_cs_swap = 0x10 + }, + [2] = { + .bdcfg_ddr_density = { 0x06, 0x06 }, + .bdcfg_ca_swap = 0x02150643, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x58264031, 0x40587236 }, + .bdcfg_dm_swap = { 0x07, 0x01 }, + .bdcfg_cs_swap = 0x10 + }, + [3] = { + .bdcfg_ddr_density = { 0x06, 0x06 }, + .bdcfg_ca_swap = 0x01546230, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x45761328, 0x68023745 }, + .bdcfg_dm_swap = { 0x00, 0x01 }, + .bdcfg_cs_swap = 0x10 + } + } +}; + +const struct renesas_dbsc5_board_config * +dbsc5_get_board_data(struct udevice *dev, const u32 modemr0) +{ + /* + * MD[19] is used to discern between 5500 Mbps and 6400 Mbps operation. + * + * Boards with 1 rank of DRAM can operate at 6400 Mbps, those are the + * Sparrow Hawk boards with 8 GiB of DRAM. Boards with 2 ranks of DRAM + * are limited to 5500 Mbps operation, those are the boards with 16 GiB + * of DRAM. + * + * Use MD[19] setting to discern 8 GiB and 16 GiB DRAM Sparrow Hawk + * board variants from each other automatically. + */ + if (modemr0 & BIT(19)) + return &renesas_v4h_sparrowhawk_16g_5500_dbsc5_board_config; + else + return &renesas_v4h_sparrowhawk_8g_6400_dbsc5_board_config; +} + +#endif + +#define RST_MODEMR0 0xe6160000 + +DECLARE_GLOBAL_DATA_PTR; + +void renesas_dram_init_banksize(void) +{ + const u32 modemr0 = readl(RST_MODEMR0); + int bank; + + /* 8 GiB device, do nothing. */ + if (!(modemr0 & BIT(19))) + return; + + /* 16 GiB device, adjust memory map. */ + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (gd->bd->bi_dram[bank].start == 0x480000000ULL) + gd->bd->bi_dram[bank].size = 0x180000000ULL; + else if (gd->bd->bi_dram[bank].start == 0x600000000ULL) + gd->bd->bi_dram[bank].size = 0x200000000ULL; + } +} diff --git a/configs/r8a779g3_sparrowhawk_defconfig b/configs/r8a779g3_sparrowhawk_defconfig new file mode 100644 index 00000000000..47fc536df81 --- /dev/null +++ b/configs/r8a779g3_sparrowhawk_defconfig @@ -0,0 +1,69 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_RENESAS=y +CONFIG_RCAR_GEN4=y +CONFIG_ARM_SMCCC=y +CONFIG_ARMV8_PSCI=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_OFFSET=0x3f80000 +CONFIG_ENV_OFFSET_REDUND=0x3fc0000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779g3-sparrow-hawk" +CONFIG_TARGET_SPARROWHAWK=y +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_CLK_FREQ=16666666 +CONFIG_SYS_BARGSIZE=2048 +CONFIG_SYS_CBSIZE=2048 +CONFIG_BAUDRATE=921600 +CONFIG_BINMAN=y +CONFIG_BOOTCOMMAND="tftp 0x50000000 fitImage && bootm 0x50000000" +CONFIG_DEFAULT_FDT_FILE="r8a779g3-sparrow-hawk.dtb" +CONFIG_CMD_REMOTEPROC=y +CONFIG_GPIO_HOG=y +CONFIG_REMOTEPROC_RENESAS_APMU=y +CONFIG_BITBANGMII=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_RENESAS_RAVB=y + +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xeb300000 +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_TEXT_BASE=0xeb210000 +CONFIG_SPL_STACK_R_ADDR=0x44000000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SPL_FIT_PRINT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x48000000 +# CONFIG_SPL_BOARD_INIT is not set +# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set +# CONFIG_SPL_SEPARATE_BSS is not set +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_SPL_GPIO=y +CONFIG_SPL_GPIO_HOG=y +CONFIG_SPL_PINCTRL=y +CONFIG_SPL_PINCONF=y +CONFIG_SPL_RAM=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_RAM=y +CONFIG_RAM_RENESAS_DBSC5=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 +CONFIG_SF_DEFAULT_SPEED=40000000 +# CONFIG_SPL_PARTITIONS is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +# CONFIG_SPL_PARTITION_UUIDS is not set +# CONFIG_SPL_DM_MMC is not set diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst index 0a38ff42eae..fedfeed42e3 100644 --- a/doc/board/renesas/renesas.rst +++ b/doc/board/renesas/renesas.rst @@ -180,6 +180,12 @@ Renesas is a SoC solutions provider for automotive and industrial applications. - arm64 - r8a779g0_whitehawk_defconfig + * - + - Sparrow Hawk + - R8A779G3 (V4H) + - arm64 + - r8a779g3_sparrowhawk_defconfig + * - RZ/G2 Family - Beacon EmbeddedWorks RZ/G2M SoM - R8A774A1 (RZ/G2M) diff --git a/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk.dts b/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk.dts new file mode 100644 index 00000000000..b109095a0d8 --- /dev/null +++ b/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk.dts @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H ES3.0 Sparrow Hawk board + * + * Copyright (C) 2025 Marek Vasut + */ + +/dts-v1/; +#include + +#include "r8a779g3.dtsi" + +/ { + model = "Retronix Sparrow Hawk board based on r8a779g3"; + compatible = "retronix,sparrow-hawk", "renesas,r8a779g3", + "renesas,r8a779g0"; + + aliases { + ethernet0 = &avb0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &hscif0; + serial1 = &hscif1; + serial2 = &hscif3; + spi0 = &rpc; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:921600n8"; + }; + + /* Page 31 / FAN */ + fan: pwm-fan { + pinctrl-0 = <&irq4_pins>; + pinctrl-names = "default"; + compatible = "pwm-fan"; + #cooling-cells = <2>; + interrupts-extended = <&intc_ex 4 IRQ_TYPE_EDGE_FALLING>; + /* + * The fan model connected to this device can be selected + * by user. Set "cooling-levels" DT property to single 255 + * entry to force the fan PWM into constant HIGH, which + * forces the fan to spin at maximum RPM, thus providing + * maximum cooling to this device and protection against + * misconfigured PWM duty cycle to the fan. + * + * User has to configure "pwms" and "pulses-per-revolution" + * DT properties according to fan datasheet first, and then + * extend "cooling-levels = <0 m n ... 255>" property to + * achieve proper fan control compatible with fan model + * installed by user. + */ + cooling-levels = <255>; + pulses-per-revolution = <2>; + pwms = <&pwm0 0 50000>; + }; + + /* + * Page 15 / LPDDR5 + * + * This configuration listed below is for the 8 GiB board variant + * with MT62F1G64D8EK-023 WT:C LPDDR5 part populated on the board. + * + * A variant with 16 GiB MT62F2G64D8EK-023 WT:C part populated on + * the board is automatically handled by the bootloader, which + * adjusts the correct DRAM size into the memory nodes below. + */ + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x1 0x00000000>; + }; + + /* Page 27 / DSI to Display */ + mini-dp-con { + compatible = "dp-connector"; + label = "CN6"; + type = "full-size"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* Page 27 / DSI to Display */ + sn65dsi86_refclk: clk-x9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + + /* Page 17 uSD-Slot */ + vcc_sdhi: regulator-vcc-sdhi { + compatible = "regulator-gpio"; + regulator-name = "SDHI VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 0>, <1800000 1>; + }; +}; + +/* Page 22 / Ether_AVB0 */ +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&avb0_phy>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + avb0_phy: ethernet-phy@0 { /* KSZ9031RNXVB */ + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + /* AVB0_PHY_INT_V */ + interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; + /* GP7_10/AVB0_RESETN_V */ + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +/* Page 28 / CANFD_IF */ +&can_clk { + clock-frequency = <40000000>; +}; + +/* Page 28 / CANFD_IF */ +&canfd { + pinctrl-0 = <&canfd3_pins>, <&canfd4_pins>, <&can_clk_pins>; + pinctrl-names = "default"; + + status = "okay"; + + channel3 { + status = "okay"; + }; + + channel4 { + status = "okay"; + }; +}; + +/* Page 27 / DSI to Display */ +&dsi1 { + status = "okay"; + + ports { + port@1 { + dsi1_out: endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +/* Page 27 / DSI to Display */ +&du { + status = "okay"; +}; + +/* Page 5 / R-Car V4H_INT_I2C */ +&extal_clk { /* X3 */ + clock-frequency = <16666666>; +}; + +/* Page 5 / R-Car V4H_INT_I2C */ +&extalr_clk { /* X2 */ + clock-frequency = <32768>; +}; + +/* Page 26 / 2230 Key M M.2 */ +&gpio4 { + /* 9FGV0441 nOE inputs 0 and 1 */ + pcie-m2-oe-hog { + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "PCIe-CLK-nOE-M2"; + }; + + /* 9FGV0441 nOE inputs 2 and 3 */ + pcie-usb-oe-hog { + gpio-hog; + gpios = <22 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "PCIe-CLK-nOE-USB"; + }; +}; + +/* Page 23 / DEBUG */ +&hscif0 { /* FTDI ADBUS[3:0] */ + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + bootph-all; + + status = "okay"; +}; + +/* Page 23 / DEBUG */ +&hscif1 { /* FTDI BDBUS[3:0] */ + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + status = "okay"; +}; + +/* Page 24 / UART */ +&hscif3 { /* CN7 pins 8 (TX) and 10 (RX) */ + pinctrl-0 = <&hscif3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +/* Page 24 / I2C SWITCH */ +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; + + mux@71 { + compatible = "nxp,pca9544"; /* TCA9544 */ + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <®_3p3v>; + + i2c0_mux0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + /* Page 27 / DSI to Display */ + bridge@2c { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; + }; + + i2c0_mux1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c0_mux2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c0_mux3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* Page 29 / CSI_IF_CN / CAM_CN0 */ +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; +}; + +/* Page 29 / CSI_IF_CN / CAM_CN1 */ +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; +}; + +/* Page 31 / IO_CN */ +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; +}; + +/* Page 31 / IO_CN */ +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; +}; + +/* Page 18 / POWER_CORE and Page 19 / POWER_PMIC */ +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&i2c5_pins>; + pinctrl-names = "default"; +}; + +/* Page 17 uSD-Slot */ +&mmc0 { + pinctrl-0 = <&sd_pins>; + pinctrl-1 = <&sd_uhs_pins>; + pinctrl-names = "default", "state_uhs"; + bus-width = <4>; + cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; /* SD_CD */ + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vcc_sdhi>; + status = "okay"; +}; + +/* Page 26 / 2230 Key M M.2 */ +&pcie0_clkref { + clock-frequency = <100000000>; +}; + +&pciec0 { + reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* Page 25 / PCIe to USB */ +&pcie1_clkref { + clock-frequency = <100000000>; +}; + +&pciec1 { + /* uPD720201 is PCIe Gen2 x1 device */ + num-lanes = <1>; + reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + /* Page 22 / Ether_AVB0 */ + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", + "avb0_txcrefclk"; + function = "avb0"; + }; + + pins-mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins-mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + + }; + + /* Page 28 / CANFD_IF */ + can_clk_pins: can-clk { + groups = "can_clk"; + function = "can_clk"; + }; + + /* Page 28 / CANFD_IF */ + canfd3_pins: canfd3 { + groups = "canfd3_data"; + function = "canfd3"; + }; + + /* Page 28 / CANFD_IF */ + canfd4_pins: canfd4 { + groups = "canfd4_data"; + function = "canfd4"; + }; + + /* Page 23 / DEBUG */ + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + /* Page 23 / DEBUG */ + hscif1_pins: hscif1 { + groups = "hscif1_data_a", "hscif1_ctrl_a"; + function = "hscif1"; + }; + + /* Page 24 / UART */ + hscif3_pins: hscif3 { + groups = "hscif3_data_a"; + function = "hscif3"; + }; + + /* Page 24 / I2C SWITCH */ + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + /* Page 29 / CSI_IF_CN / CAM_CN0 */ + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + /* Page 29 / CSI_IF_CN / CAM_CN1 */ + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + /* Page 31 / IO_CN */ + i2c3_pins: i2c3 { + groups = "i2c3"; + function = "i2c3"; + }; + + /* Page 31 / IO_CN */ + i2c4_pins: i2c4 { + groups = "i2c4"; + function = "i2c4"; + }; + + /* Page 18 / POWER_CORE */ + i2c5_pins: i2c5 { + groups = "i2c5"; + function = "i2c5"; + }; + + /* Page 27 / DSI to Display */ + irq0_pins: irq0 { + groups = "intc_ex_irq0_a"; + function = "intc_ex"; + }; + + /* Page 31 / FAN */ + irq4_pins: irq4 { + groups = "intc_ex_irq4_b"; + function = "intc_ex"; + }; + + /* Page 31 / FAN */ + pwm0_pins: pwm0 { + groups = "pwm0"; + function = "pwm0"; + }; + + /* Page 31 / CN7 pin 12 */ + pwm1_pins: pwm1 { + groups = "pwm1_b"; + function = "pwm1"; + }; + + /* Page 31 / CN7 pin 32 */ + pwm6_pins: pwm6 { + groups = "pwm6"; + function = "pwm6"; + }; + + /* Page 31 / CN7 pin 33 */ + pwm7_pins: pwm7 { + groups = "pwm7"; + function = "pwm7"; + }; + + /* Page 16 / QSPI_FLASH */ + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + bootph-all; + }; + + /* Page 6 / SCIF_CLK_SOC_V */ + scif_clk_pins: scif-clk { + groups = "scif_clk"; + function = "scif_clk"; + }; + + /* Page 17 uSD-Slot */ + sd_pins: sd { + groups = "mmc_data4", "mmc_ctrl"; + function = "mmc"; + power-source = <3300>; + }; + + /* Page 17 uSD-Slot */ + sd_uhs_pins: sd-uhs { + groups = "mmc_data4", "mmc_ctrl"; + function = "mmc"; + power-source = <1800>; + }; +}; + +/* Page 31 / FAN */ +&pwm0 { + pinctrl-0 = <&pwm0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Page 31 / CN7 pin 12 */ +&pwm1 { + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Page 31 / CN7 pin 32 */ +&pwm6 { + pinctrl-0 = <&pwm6_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Page 31 / CN7 pin 33 */ +&pwm7 { + pinctrl-0 = <&pwm7_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Page 16 / QSPI_FLASH */ +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + bootph-all; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x0 0x1000000>; + read-only; + }; + + user@1000000 { + reg = <0x1000000 0x2f80000>; + }; + + env1@3f80000 { + reg = <0x3f80000 0x40000>; + }; + + env2@3fc0000 { + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +/* Page 6 / SCIF_CLK_SOC_V */ +&scif_clk { /* X12 */ + clock-frequency = <24000000>; +}; diff --git a/include/configs/sparrowhawk.h b/include/configs/sparrowhawk.h new file mode 100644 index 00000000000..0524e39229c --- /dev/null +++ b/include/configs/sparrowhawk.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/sparrowhawk.h + * This file is Sparrow Hawk board configuration. + * + * Copyright (C) 2025 Marek Vasut + */ + +#ifndef __SPARROWHAWK_H +#define __SPARROWHAWK_H + +#include "rcar-gen4-common.h" + +#endif /* __SPARROWHAWK_H */ -- 2.39.5