From 532fd00bdb763748d1c52f37203f3e04dbd4276a Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Sun, 3 Aug 2025 18:24:28 -0700 Subject: [PATCH] drivers: clk: agilex: Use real clock source frequency Update the ARMv8 generic timer frequency register (cntfrq_el0) with the actual hardware timer frequency (COUNTER_FREQUENCY_REAL). The generic timer frequency was set to 0x200000000 during boot clk which needs to be set to 0x400000000 when transition from boot clk to PLL clk. This will ensure that subsequent timer operations are based on the correct frequency, ensuring accurate timekeeping. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- drivers/clk/altera/clk-agilex.c | 13 +++++++++++++ drivers/clk/altera/clk-agilex.h | 2 ++ 2 files changed, 15 insertions(+) diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index e1ddd02f356..b922723d8da 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -337,6 +338,18 @@ static void clk_basic_init(struct udevice *dev, CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST, CLKMGR_ALT_EXTCNTRST_ALLCNTRST); +#ifdef COUNTER_FREQUENCY_REAL + u32 cntfrq = COUNTER_FREQUENCY_REAL; + u32 counter_freq = 0; + + /* Update with accurate clock frequency */ + if (current_el() == 3) { + asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); + asm volatile("mrs %0, cntfrq_el0" : "=r" (counter_freq)); + debug("Counter freq = 0x%x\n", counter_freq); + } +#endif + /* Out of boot mode */ clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); diff --git a/drivers/clk/altera/clk-agilex.h b/drivers/clk/altera/clk-agilex.h index cd68ebc4387..b3e8841a512 100644 --- a/drivers/clk/altera/clk-agilex.h +++ b/drivers/clk/altera/clk-agilex.h @@ -10,6 +10,8 @@ #include #endif +#define COUNTER_FREQUENCY_REAL 400000000 + #define CM_REG_READL(plat, reg) \ readl((plat)->regs + (reg)) -- 2.47.2