From 4c020a961a812ffae9846b917304cea504c3a733 Mon Sep 17 00:00:00 2001
From: David Dillow <dave@thedillows.org>
Date: Wed, 3 Mar 2010 16:33:10 +0000
Subject: [PATCH] r8169: use correct barrier between cacheable and
 non-cacheable memory

r8169 needs certain writes to be visible to other CPUs or the NIC before
touching the hardware, but was using smp_wmb() which is only required to
order cacheable memory access. Switch to wmb() which is required to
order both cacheable and non-cacheable memory.

Noticed by Catalin Marinas and Paul Mackerras.

Signed-off-by: David Dillow <dave@thedillows.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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