From 497a92308af8e9385fa3d135f7f416a997e4b93b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 15 May 2014 16:59:34 +0200 Subject: [PATCH] ARM: mvebu: implement L2/PCIe deadlock workaround The Marvell Armada 375 and Armada 38x SOCs, which use the Cortex-A9 CPU core, the PL310 cache and the Marvell PCIe hardware block are affected a L2/PCIe deadlock caused by a system erratum when hardware I/O coherency is used. This deadlock can be avoided by mapping the PCIe memory areas as strongly-ordered (note: MT_UNCACHED is strongly-ordered), and by removing the outer cache sync done in software. This is implemented in this patch by: * Registering a custom arch_ioremap_caller function that allows to make sure PCI memory regions are mapped MT_UNCACHED. * Adding at runtime the 'arm,io-coherent' property to the PL310 cache controller. This cannot be done permanently in the DT, because the hardware I/O coherency can only be enabled when CONFIG_SMP is enabled, in the current kernel situation. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1400165974-9059-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- Reading git-format-patch failed