From 46c291e14779d83cb216c9177cf7bb327005382b Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 26 Feb 2025 11:37:11 +0000 Subject: [PATCH] sunxi: mmc: Fix T113-s3 MMC clock divider MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit On the Allwinner D1/R528/T113-s3 SoCs the MMC clock source selected by mux value 1 is PLL_PERIPH0(1x), not (2x), as in the other SoCs. But we have still the hidden divisor of 2 in the MMC mod clock, so need to explicitly compensate for that on those SoCs. This leads to the actually programmed clock rate to be double compared to before, which increases the MMC performance on those SoCs. Signed-off-by: Andre Przywara Reported-by: Kuba Szczodrzyński Reviewed-by: Jernej Skrabec Reviewed-by: Peng Fan --- drivers/mmc/sunxi_mmc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 0b56d1405be..8f72d758e46 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -92,6 +92,13 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) pll = CCM_MMC_CTRL_PLL6; pll_hz = clock_get_pll6(); #endif + /* + * On the D1/R528/T113 mux source 1 refers to PLL_PERIPH0(1x), + * like for the older SoCs. However we still have the hidden + * divider of 2x, so compensate for that here. + */ + if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) + pll_hz /= 2; } div = pll_hz / hz; -- 2.39.5