From 44991eb4bfd63b043b50e880d347a7946d6a9736 Mon Sep 17 00:00:00 2001
From: Jisheng Zhang <jszhang@marvell.com>
Date: Thu, 12 Jun 2014 17:38:40 +0800
Subject: [PATCH] ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles

For all BG2Q SoCs, 2 cycles is the best/correct value.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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