From 40a5dcba4e79023f0b511dc0ca498bdf9eacb5db Mon Sep 17 00:00:00 2001
From: =?utf8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
Date: Mon, 23 Dec 2013 00:32:32 -0300
Subject: [PATCH] clk: sunxi: register factors clocks behind composite
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This commit reworks factors clock registration to be done behind a
composite clock. This allows us to additionally add a gate, mux or
divisors, as it will be needed by some future PLLs.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
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