From 3d9e6d42ca1433c6dd478bf6c0f73e2b9484c94c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 24 Apr 2025 11:16:41 +0200 Subject: [PATCH] clk: qcom: apq8016: Fix SDCC clock addresses The SDCC_...(n) macros in clock-apq8016.c result in the wrong addresses: - SDCC1: SDCC_APPS_CBCR(0) = ((0 * 0x1000) + 0x41018) = 0x41018 Should be 0x42018, this is an invalid register close to the USB clocks. - SDCC2: SDCC_APPS_CBCR(1) = ((1 * 0x1000) + 0x41018) = 0x42018 Should be 0x43018, this is the SDCC1 clock. When we try to enable SDCC2, we actually end up enabling SDCC1. When we try to enable SDCC1, we just issue some broken register writes. This hasn't caused any trouble so far, because the boot firmware is keeping both SDCC clocks running. However, if these clocks are disabled when entering U-Boot, MMC initialization is failing. Fix this by using the proper offset for the macros. The SDCC_CMD_RCGR() was already correct, but change it the same way for consistency. Fixes: 085921368b7d ("arm: Add support for Qualcomm Snapdragon family") Reviewed-by: Neil Armstrong Signed-off-by: Stephan Gerhold Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-1-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-apq8016.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 6a53f900a9e..274c71c53ff 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -23,10 +23,10 @@ #define APCS_GPLL_ENA_VOTE (0x45000) #define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) -#define SDCC_BCR(n) ((n * 0x1000) + 0x41000) -#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004) -#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) -#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) +#define SDCC_BCR(n) (((n) * 0x1000) + 0x42000) +#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x42004) +#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x42018) +#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4201C) /* BLSP1 AHB clock (root clock for BLSP) */ #define BLSP1_AHB_CBCR 0x1008 -- 2.39.5