From 3818f11740bbf87ad76f4f502f6739c8d62e5c17 Mon Sep 17 00:00:00 2001
From: Tomasz Figa <t.figa@samsung.com>
Date: Tue, 15 Oct 2013 19:41:18 +0200
Subject: [PATCH] clk: samsung: exynos5250: Fix parent of gate clocks from
 DISP1 domain

This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC
documentation is the correct parent of DISP1 gate clocks.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
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