From 2e93cac90c4b063c8732deb727a192dea1119640 Mon Sep 17 00:00:00 2001
From: =?utf8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
Date: Fri, 16 May 2014 11:10:29 +0200
Subject: [PATCH] drm/radeon/hdmi: DCE3: clean ACR control
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What initially seemed to be a typo in fglrx (using register 0x740c
instead of 0x74dc) appeared to be a correct behavior. DCE3 has ACR and
CRC registers swapped which explains why we needed
WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);

This has been tested for possible regressions on DCE3 HD3470 (RV620).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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