From 2e523e98bb593950de2c749d4ceb45cc20313c1a Mon Sep 17 00:00:00 2001
From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Fri, 10 Apr 2015 18:21:27 +0300
Subject: [PATCH] drm/i915: Implement chv display PHY lane stagger setup
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Set up the chv display PHY lane stagger registers according to
"Programming Guide for 1273 CHV eDP/DP/HDMI Display PHY" v1.04

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by:  Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
Reading git-format-patch failed