From 25c9ded6ed31184379c9b153ff37621fc323b084 Mon Sep 17 00:00:00 2001
From: Paul Walmsley <pwalmsley@nvidia.com>
Date: Fri, 7 Jun 2013 06:18:58 -0600
Subject: [PATCH] clk: tegra: T114: add FCPU clock shaper programming, needed
 by the DFLL

Add clock functions to initialize, enable, and disable the FCPU clock
shapers, based on the FCPU voltage rail state.  These will be used by
the DFLL clocksource driver code.

This version of the patch contains a fix for a problem noticed by Andrew
Chew <achew@nvidia.com>, where some of the FINETRIM_R bitfields were
incorrectly defined.

Based on code originally written by Aleksandr Frid <afrid@nvidia.com>.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Andrew Chew <achew@nvidia.com>
Reviewed-by: Andrew Chew <achew@nvidia.com>
Cc: Matthew Longnecker <mlongnecker@nvidia.com>
Cc: Aleksandr Frid <afrid@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
---
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