From 24a01453892e0a4a6ad38460541bd0dae9b1837f Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Date: Tue, 30 Jan 2007 20:40:30 +0300
Subject: [PATCH] pata_sl82c105: wrong assumptions about compatible PIO modes

Fix the wrong "compatible" PIO mode choices: MWDMA0 has 480 ns cycle while PIO1
only has 383 ns cycle, and MWDMA2 timings matchs those of PIO4 exactly.

Signed-off-by: Jeff Garzik <jeff@garzik.org>
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