From 1b333e40630f42173270b964ed69be494c2df53a Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Sat, 1 Nov 2025 03:44:55 +0300 Subject: [PATCH] reset: airoha: add support for airoha en7523 SoC family This adds reset controller support for airoha en7523/en7529/en7562 SoCs. Signed-off-by: Mikhail Kshevetskiy --- drivers/reset/reset-airoha.c | 71 ++++++++++++++++++++++++++++++++++-- 1 file changed, 68 insertions(+), 3 deletions(-) diff --git a/drivers/reset/reset-airoha.c b/drivers/reset/reset-airoha.c index 58b868d9855..ef8c47a067b 100644 --- a/drivers/reset/reset-airoha.c +++ b/drivers/reset/reset-airoha.c @@ -13,6 +13,7 @@ #include #include +#include #include #define RST_NR_PER_BANK 32 @@ -23,6 +24,7 @@ struct airoha_reset_priv { const u16 *bank_ofs; const u16 *idx_map; + int num_rsts; struct regmap *map; }; @@ -31,6 +33,53 @@ static const u16 en7581_rst_ofs[] = { REG_RESET_CONTROL1, }; +static const u16 en7523_rst_map[] = { + /* RST_CTRL2 */ + [EN7523_XPON_PHY_RST] = 0, + [EN7523_XSI_MAC_RST] = 7, + [EN7523_XSI_PHY_RST] = 8, + [EN7523_NPU_RST] = 9, + [EN7523_I2S_RST] = 10, + [EN7523_TRNG_RST] = 11, + [EN7523_TRNG_MSTART_RST] = 12, + [EN7523_DUAL_HSI0_RST] = 13, + [EN7523_DUAL_HSI1_RST] = 14, + [EN7523_HSI_RST] = 15, + [EN7523_DUAL_HSI0_MAC_RST] = 16, + [EN7523_DUAL_HSI1_MAC_RST] = 17, + [EN7523_HSI_MAC_RST] = 18, + [EN7523_WDMA_RST] = 19, + [EN7523_WOE0_RST] = 20, + [EN7523_WOE1_RST] = 21, + [EN7523_HSDMA_RST] = 22, + [EN7523_I2C2RBUS_RST] = 23, + [EN7523_TDMA_RST] = 24, + /* RST_CTRL1 */ + [EN7523_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, + [EN7523_FE_PDMA_RST] = RST_NR_PER_BANK + 1, + [EN7523_FE_QDMA_RST] = RST_NR_PER_BANK + 2, + [EN7523_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, + [EN7523_CRYPTO_RST] = RST_NR_PER_BANK + 6, + [EN7523_TIMER_RST] = RST_NR_PER_BANK + 8, + [EN7523_PCM1_RST] = RST_NR_PER_BANK + 11, + [EN7523_UART_RST] = RST_NR_PER_BANK + 12, + [EN7523_GPIO_RST] = RST_NR_PER_BANK + 13, + [EN7523_GDMA_RST] = RST_NR_PER_BANK + 14, + [EN7523_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, + [EN7523_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, + [EN7523_SFC_RST] = RST_NR_PER_BANK + 18, + [EN7523_UART2_RST] = RST_NR_PER_BANK + 19, + [EN7523_GDMP_RST] = RST_NR_PER_BANK + 20, + [EN7523_FE_RST] = RST_NR_PER_BANK + 21, + [EN7523_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, + [EN7523_GSW_RST] = RST_NR_PER_BANK + 23, + [EN7523_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, + [EN7523_PCIE0_RST] = RST_NR_PER_BANK + 26, + [EN7523_PCIE1_RST] = RST_NR_PER_BANK + 27, + [EN7523_PCIE_HB_RST] = RST_NR_PER_BANK + 29, + [EN7523_XPON_MAC_RST] = RST_NR_PER_BANK + 31, +}; + static const u16 en7581_rst_map[] = { /* RST_CTRL2 */ [EN7581_XPON_PHY_RST] = 0, @@ -136,7 +185,7 @@ static int airoha_reset_xlate(struct reset_ctl *reset_ctl, { struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev); - if (args->args[0] >= ARRAY_SIZE(en7581_rst_map)) + if (args->args[0] >= priv->num_rsts) return -EINVAL; reset_ctl->id = priv->idx_map[args->args[0]]; @@ -151,7 +200,7 @@ static struct reset_ops airoha_reset_ops = { .rst_status = airoha_reset_status, }; -static int airoha_reset_probe(struct udevice *dev) +static int reset_init(struct udevice *dev, const u16 *rst_map, int num_rsts) { struct airoha_reset_priv *priv = dev_get_priv(dev); @@ -160,11 +209,27 @@ static int airoha_reset_probe(struct udevice *dev) return PTR_ERR(priv->map); priv->bank_ofs = en7581_rst_ofs; - priv->idx_map = en7581_rst_map; + priv->idx_map = rst_map; + priv->num_rsts = num_rsts; return 0; } +static int airoha_reset_probe(struct udevice *dev) +{ + if (ofnode_device_is_compatible(dev_ofnode(dev), + "airoha,en7523-scu")) + return reset_init(dev, en7523_rst_map, + ARRAY_SIZE(en7523_rst_map)); + + if (ofnode_device_is_compatible(dev_ofnode(dev), + "airoha,en7581-scu")) + return reset_init(dev, en7581_rst_map, + ARRAY_SIZE(en7581_rst_map)); + + return -ENODEV; +} + U_BOOT_DRIVER(airoha_reset) = { .name = "airoha-reset", .id = UCLASS_RESET, -- 2.47.3