From 173701d7745d07888a929bf08d77d29996ca13dc Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Wed, 9 Nov 2011 15:39:58 +0100
Subject: [PATCH] microblaze: Clear all MSR flags on the first kernel
 instruction

The main reason is bug because of dynamic TLB allocation.
U-BOOT didn't disable dcache and then writing to physical address
from ASM wan't visible for reading through MMU.
Disabling caches and clearing all flags from previous code
is good to do so.

Signed-off-by: Michal Simek <monstr@monstr.eu>
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