From 1561b01a0851e9ada026778c5518f0bef8caa3e3 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Mon, 7 Apr 2025 19:56:14 +0200 Subject: [PATCH] clk/qcom: apq8096: fix set rate for the uart clock The function should return a valid rate. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Neil Armstrong Reviewed-by: Caleb Connolly Reviewed-by: Link: https://lore.kernel.org/r/20250407175617.3494506-2-jorge.ramirez@oss.qualcomm.com Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-apq8096.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index c77d69128b0..bc00826a5e8 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -87,7 +87,8 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate) return clk_init_sdc(priv, rate); break; case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/ - return clk_init_uart(priv); + clk_init_uart(priv); + return 7372800; default: return 0; } -- 2.39.5