From 0783a56087e9ecfae2f01f9662ff52081c5b5e25 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Tue, 19 Aug 2014 15:21:12 -0300
Subject: [PATCH] ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks

PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and
PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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