From 0691bb1b5a1865b3bbc9b7ce6e26eff546abb1cf Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@altera.com>
Date: Mon, 12 May 2014 12:27:22 -0500
Subject: [PATCH] clk: socfpga: add divider registers to the main pll outputs

The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
PLL go through a pre-divider before coming into the system. These registers
were hidden for the CycloneV platform, but are now used for the ArriaV
platform.

This patch updates the clock driver to read the div-reg property for the
socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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