From 034fbcc3d8a5dff5d3df5a4ad6bf9cc0b01bd970 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@gmail.com>
Date: Wed, 25 Jun 2014 09:54:36 -0400
Subject: [PATCH] drm/msm: hdmi phy 8960 phy pll

On downstream kernel the clk driver directly bangs hdmi phy registers.
For upstream kernel, we need to model this as a clock and register with
the clock framework.

Signed-off-by: Rob Clark <robdclark@gmail.com>
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