From 02933626c7351db6f38cd72d85b47188655fbc85 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Fri, 7 Mar 2025 17:11:45 +0000 Subject: [PATCH] clk: sophgo: Fix return values of register updating helpers These helpers wrongly return the updated register value. As a non-zero value indicates failure, this causes various clock operations are considered failed. Correct the return value to constant zero, since these simple MMIO operations won't fail. This fixes clock enabling failures during booting process, In: serial@4140000 Out: serial@4140000 Err: serial@4140000 Net: Enable clock-controller@3002000 failed failed to enable clock 0 No ethernet found. which leads to misoperation of various peripherals. Fixes: 5f364e072e7 ("clk: sophgo: cv1800b: Add clock controller driver for cv1800b SoC") Tested-by: Yuguo Pei Signed-off-by: Yao Zi --- drivers/clk/sophgo/clk-common.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sophgo/clk-common.h b/drivers/clk/sophgo/clk-common.h index 95b82e968d0..a9e83d0d689 100644 --- a/drivers/clk/sophgo/clk-common.h +++ b/drivers/clk/sophgo/clk-common.h @@ -45,12 +45,14 @@ static inline u32 cv1800b_clk_getbit(void *base, struct cv1800b_clk_regbit *bit) static inline u32 cv1800b_clk_setbit(void *base, struct cv1800b_clk_regbit *bit) { - return setbits_le32(base + bit->offset, BIT(bit->shift)); + setbits_le32(base + bit->offset, BIT(bit->shift)); + return 0; } static inline u32 cv1800b_clk_clrbit(void *base, struct cv1800b_clk_regbit *bit) { - return clrbits_le32(base + bit->offset, BIT(bit->shift)); + clrbits_le32(base + bit->offset, BIT(bit->shift)); + return 0; } static inline u32 cv1800b_clk_getfield(void *base, -- 2.39.5