From 021f653791ad17e03f98aaa7fb933816ae16f161 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Mon, 30 Jun 2014 16:01:31 +0100 Subject: [PATCH] irqchip: gic-v3: Initial support for GICv3 The Generic Interrupt Controller (version 3) offers services that are similar to GICv2, with a number of additional features: - Affinity routing based on the CPU MPIDR (ARE) - System register for the CPU interfaces (SRE) - Support for more that 8 CPUs - Locality-specific Peripheral Interrupts (LPIs) - Interrupt Translation Services (ITS) This patch adds preliminary support for GICv3 with ARE and SRE, non-secure mode only. It relies on higher exception levels to grant ARE and SRE access. Support for LPI and ITS will be added at a later time. Cc: Thomas Gleixner Cc: Jason Cooper Reviewed-by: Zi Shen Lim Reviewed-by: Christoffer Dall Reviewed-by: Tirumalesh Chalamarla Reviewed-by: Yun Wu Reviewed-by: Zhen Lei Tested-by: Tirumalesh Chalamarla Tested-by: Radha Mohan Chintakuntla Acked-by: Radha Mohan Chintakuntla Acked-by: Catalin Marinas Signed-off-by: Marc Zyngier Reviewed-by: Mark Rutland Link: https://lkml.kernel.org/r/1404140510-5382-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper --- Reading git-format-patch failed