From 00c674e42c278e7af7b39b6c72dbbaa5e7ebd96c Mon Sep 17 00:00:00 2001
From: Thierry Reding <thierry.reding@gmail.com>
Date: Mon, 18 Nov 2013 16:11:35 +0100
Subject: [PATCH] clk: tegra: Fix clock rate computation

The PLL output frequency is multiplied during the P-divider computation,
so it needs to be divided by the P-divider again before returning.

This fixes an issue where clk_round_rate() would return the multiplied
frequency instead of the real one after the P-divider.

Signed-off-by: Thierry Reding <treding@nvidia.com>
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